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PCI-SIG specifications define standards driving the industry-wide compatibility of peripheral component interconnects. Members regularly review them, providing commentary and change requests when necessary. These requests are considered by technical workgroups and applied as appropriate, resulting in collaboratively devised specifications benefiting millions of platforms and add-in devices.
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The connector and cable assembly pinout tables have been revised to show the complete OCuLink pinout assignments in all cases. The two left-most columns in the cable pinout tables have been combined for clarity. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been included in the appropriate column titles of the cable pinout tables to make it easier to follow which end of the cable is being addressed on each page in each table. Show less 1.x ECN October 6, 2017.
The connector and cable assembly pinout tables have been revised to show the complete OCuLink pinout assignments in all cases. The two left-most columns in the cable pinout tables have been combined for clarity. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been included in the appropriate column titles of the cable pinout tables to make it easier to follow which end of the cable is being addressed on each page in each table. Show less 1.x ECN October 6, 2017. This ECN specifies changes to the PCI Local Bus Spec.
View more This ECN specifies changes to the PCI Local Bus Specification Revision 3.0 and the PCI Express CEM Specification 3.0. Changes to the PCI Local Bus Specification cover a new VPD encoding and a 32-bit field. Changes to the PCI Express CEM Specification cover a series of graphs used to classify air flow impedance and thermal properties under varying conditions as well as the test figure and process to create these graphs for a given adapter add-in card. Adapter add-in card types supported by this include all SINGLE-SLOT and DUAL-SLOT PCIe CEM adapter add-in cards without integrated air movers, including standard height adapter add-in cards as well as low-profile adapter add-in cards). Adapter add-in cards with an integrated air mover were not addressed due to the added complication of their integrated air mover in the overall platform’s potential cooling redundancy. Show less 3.x ECN May 31, 2017.
Defines a new, optional PCI-SIG Defined Type 1 Vendo. View more Defines a new, optional PCI-SIG Defined Type 1 Vendor Defined Message. This message provides software and/or firmware, running on a Function, additional information to uniquely identify that Function, within a large system or a collection of systems. When a single system contains multiple PCI Express Hierarchies, this message tells a Function which Hierarchy it resides in.
This value, in conjunction with the Routing ID number uniquely identifies a Function within that system. In clustered system, this message can include a System Globally Unique Identifier (System GUID) for each system.
This value, in conjunction with the Hierarchy ID and Routing ID uniquely identifies a Function within that cluster. Show less 3.x ECN March 17, 2017. M.2 Key B (WWAN) is modified to enable PCIe and USB. View more M.2 Key B (WWAN) is modified to enable PCIe and USB 3.1 Gen1 signals to be simultaneously present on the connector. This enables support for a single SKU M.2 card that supports both PCIe and USB 3.1 Gen1. There are two implementation options enabled: 1. State #14 in the “Socket 2 Add-in Card Configuration Table” is re-defined to indicate an Add-in Card built to the PCI Express M.2 Specification, Revision 1.1 or later where both PCIe and USB 3.1 Gen1 are both present on the connector.
The choice of Port Configuration is vendor defined. This enables the host to unambiguously determine that PCIe and USB 3.1 Gen1 are present on the connector. States #4, 5, 6, 7 in the “Socket 2 Add-in Card Configuration Table” are re-defined to indicate that in addition to USB 3.1 Gen1, PCIe may be present on the connector. This definition was used by M.2 cards built to the PCI Express M.2 Specification, Revision 1.0 (USB 3.1 Gen1 on connector; PCIe is “no connect”). This definition is now also permitted to be used by M.2 cards built to PCI Express M.2 Specification, Revision 1.1 or later to indicate that PCIe and USB 3.1 Gen1 are both present on the connector. This allows GPIO port configurations to remain consistent with all other existing states.
Show less 1.x ECN March 17, 2017. This ECR is intended to address a class of issues wi.
View more This ECR is intended to address a class of issues with PCI/PCIe architecture that relate to resource allocation inefficiency. To explain this, first we must define some terms: Static use cases, refer to scenarios where resources are allocated at system boot and then typically not changed again Dynamic use cases, refer to scenarios where run-time resource rebalancing (allocation of new resources, freeing of resources no longer needed) is required, due to hot add/remove, or by other needs.
In the Static cases there are limits on the size of hierarchies and number of Endpoints due to the Bus & Device Number “waste” caused by the PCI/PCIe architectural definition for Switches, and by the requirement that Downstream Ports associate an entire Bus Number with their Link. This proposal addresses this class of problems by “flattening” the use of Routing IDs so that Switches and Downstream Ports are able to make more efficient use of the available space. Show less 3.x ECN February 15, 2017. A PCI Express Receiver is required to tolerate 6 ns. View more A PCI Express Receiver is required to tolerate 6 ns of lane to lane skew when operating at 8.0 GT/s. The PCI Express OCuLink Specification allowed the cable assembly to consume the entire budget.
The Transmitter and traces routing to the OCuLink connector need some of this budget. The PCI Express Card Electromechanical Specification Revision 3.0 assigns 1.6 ns to the total interconnect lane to lane skew budget. Show less 1.x ECN December 20, 2016.
This specification defines an implementation for sma. View more This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
Show less 2.x Specification December 15, 2016. This specification defines an implementation for sma. View more This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. Show less 2.x Specification December 15, 2016 1.x Errata November 4, 2016. This ECN defines two sets of related changes to supp.
View more This ECN defines two sets of related changes to support an Emergency Power Reduction mechanism and to provide software visibility for this mechanism: 1. The Card Electromechanical Specification is updated to define an optional Emergency Power Reduction mechanism using RSVD pin B30. The PCI Express Base Specification is updated to define an optional mechanism to indicate support for Emergency Power Reduction and to provide visibility as to the power reduction status of a Device. Show less 3.x ECN December 1, 2015. This ECN is intended to define a new form-factor. View more This ECN is intended to define a new form-factor and electrical pinout to the M.2 family.
This proposal will allow PCIe and SATA to be delivered using a BGA package, expanding the use of the PCIe and SATA protocols in small form-factor applications. The new BGA pinout content is based on the Socket 3 Key-M definitions. BGA pinout supports additional pins than defined for Socket-3, for soldered-down form-factors. Show less 1.x ECN November 10, 2015.
This document is a companion Specification to the PC. View more This document is a companion Specification to the PCI Express Base Specification and other PCI Express® 2 documents listed in Section 1.1. The primary focus of the PCI Express OCuLink Specification is the implementation 3 of internal and external small form factor PCI Express® connectors and cables optimized for the client and mobile 4 market segments. This Specification discusses cabling and connector requirements to meet the 8.0 GT/s signaling 5 needs in the PCI Express Base Specification. 6 No assumptions are made regarding the implementation of PCI Express compliant components on either side of 7 the Link; such components are addressed in other PCI Express Specifications. Show less 1.x Specification October 23, 2015. The proposed change is to include 2 GNSS Aiding sign.
View more The proposed change is to include 2 GNSS Aiding signals, that we already have allocated in the Type 1216 pinout, to the Socket 1 Key E pinout and Type 2226/3026 pinout. Due to lack of free pins in the Key E pinout, it is proposed to define 2 SDIO Input signals as dual functional pins. They would be defined with their original SDIO functionality along with and alternate GNSS Aiding signals functionality to enable a GNSS solution on Type 2230 solutions on Socket 1 Key E solutions. The GNSS signals to be added are the Tx Blanking and SYSCLK signals and it is suggested to overlay them on the SDIO RESET# and SDIO CLK respectively which are also inputs. In this way it is less likely to cause a potential contention. Show less 1.x ECN October 19, 2014.
This document primarily covers PCI Express testing o. View more This document primarily covers PCI Express testing of all defined PCI Express Device Types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification and Chapter 7 of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description). Show less 3.x Specification June 6, 2013. This test specification primarily covers testing of.
View more This test specification primarily covers testing of PCI Express Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root Complex Event Collectors) are not tested under this test specification. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements. Show less 3.x Specification June 6, 2013. The PCI Express 3.0 describes a method to simulate 8. View more The PCI Express 3.0 describes a method to simulate 8GT/s channel compliance using a statistical data eye simulator.
To help members perform this simulation, a free open source tool called Seasim is provided below. This tool has been tested by members of the Electrical Working Group on multiple channels and has reached version 0.54 which should be useful for members designing 8GT/s systems. Show less 3.x Specification January 1, 2013. This optional normative ECN defines enhancements to.
View more This optional normative ECN defines enhancements to the Downstream Port Containment (DPC) ECN, an ECN that enabled automatic disabling of the Link below a Downstream Port following an uncorrectable error. The DPC ECN defined functionality for both Switch Downstream Ports and Root Ports.
This ECN mostly defines functionality that is specific to Root Ports, functionality referred to as “RP Extensions for DPC”. Show less 3.x ECN November 15, 2012. This test specification primarily covers testing of. View more This test specification primarily covers testing of all PCI Express Port types for compliance with the link layer requirements in Chapter 3 of the PCI Express Base Specification. At this point, this specification does not describe the full set of PCI Express tests for all link layer requirements. Going forward, as the testing gets mature, it is expected that more tests may be added as deemed necessary.
Show less 2.x Specification September 17, 2012. This is a companion specification to the PCI Express.
View more This is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications.
Show less 2.x Specification June 22, 2012. This is a companion specification to the PCI Express. View more This is a companion specification to the PCI Express Base Specification.
Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications. Show less 2.x Specification June 22, 2012. This ECN defines a new error containment mechanism f. View more This ECN defines a new error containment mechanism for Downstream Ports as well as minor enhancements that improve asynchronous card removal.
Downstream Port Containment (DPC) is the automatic disabling of the Link below a Downstream Port following an uncorrectable error. This prevents the potential spread of data corruption (all TLPs subsequent to the error are prevented from propagating either Upstream or Downstream) and enables error recovery if supported by software. Show less 3.x ECN February 9, 2012.
This optional normative ECN defines an End-End TLP P. View more This optional normative ECN defines an End-End TLP Prefix for conveying additional attributes associated with a request. The PASID TLP Prefix is an End-End TLP Prefix as defined in the PCI Express Base Specification.
Routing elements that support End-End TLP Prefixes (i.e. Have the End-End TLP Prefix Supported bit Set in the Device Capabilities 2 register) can correctly forward TLPs containing a PASID TLP Prefix. Show less 1.x ECN March 31, 2011 2.x Errata November 18, 2010. This ECR proposes to add a new mechanism for platfor. View more This ECR proposes to add a new mechanism for platform central resource (RC) power state information to be communicated to Devices. This mechanism enables Optimized Buffer Flush/Fill (OBFF) by allowing the platform to indicate optimal windows for device bus mastering & interrupt activity.
Devices can use internal buffering to shape traffic to fit into these optimal windows, reducing platform power impact. Show less 2.x ECN April 30, 2009. This specification describes the extensions required. View more This specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device.
The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure. This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs. Show less 1.x Specification January 26, 2009. This optional normative ECR defines a mechanism by w. View more This optional normative ECR defines a mechanism by which a Requester can provide hints on a per transaction basis to facilitate optimized processing of transactions that target Memory Space. The architected mechanisms may be used to enable association of system processing resources (e.g. Caches) with the processing of Requests from specific Functions or enable optimized system specific (e.g.
System interconnect and Memory) processing of Requests. Show less 2.x ECN September 11, 2008. This document contains a list of Test Assertions. View more This document contains a list of Test Assertions and a set of Test Definitions pertaining to the Transaction Layer.
Assertions are statements of spec requirements which are measured by the algorithm details as specified in the Test Definitions. “Basic Functional Tests” are Test Algorithms which perform basic tests for key elements of Transaction Layer device functionality. This document does not describe a full set of PCI Express tests and assertions and is in no way intended to measure products for full design validation.
Tests described here should be viewed as tools to checkpoint the result of product validation – not as a replacement for that effort. Show less 2.x Specification August 11, 2008. The purpose of this document is to specify PCI® I/O.
View more The purpose of this document is to specify PCI® I/O virtualization and sharing technology. The specification is focused on multi-root topologies; e.g., a server blade enclosure that uses a PCI Express® Switch-based topology to connect server blades to PCI Express Devices or PCI Express to-PCI Bridges and enable the leaf Devices to be serially or simultaneously shared by one or more System Images (SI).
Unlike the Single Root IOV environment, independent SI may execute on disparate processing components such as independent server blades. Show less 1.x Specification May 12, 2008. This optional normative ECN adds Multicast functiona. View more This optional normative ECN adds Multicast functionality to PCI Express by means of an Extended Capability structure for applicable Functions in Root Complexes, Switches, and components with Endpoints. The Capability structure defines how Multicast TLPs are identified and routed.
It also provides means for checking and enforcing send permission with Function-level granularity. The ECN identifies Multicast errors and adds an MC Blocked TLP error to AER for reporting those errors. Show less 2.x ECN May 8, 2008.
For virtualized and non-virtualized environments, a. View more For virtualized and non-virtualized environments, a number of PCI-SIG member companies have requested that the current constraints on number of Functions allowed per multi-Function Device be increased to accommodate the needs of next generation I/O implementations. This ECR specifies a new method to interpret the Device Number and Function Number fields within Routing IDs, Requester IDs, and Completer IDs, thereby increasing the number of Functions that can be supported by a single Device. Show less 2.x ECN June 4, 2007. This specification is a companion for the PCI Expres. View more This specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications.
The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications. Show less 2.x Specification April 11, 2007. This specification is a companion for the PCI Expres.
View more This specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications.
Show less 2.x Specification April 11, 2007. This specification describes the extensions required. View more This specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device. The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure.
This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs. Show less 1.x Specification March 8, 2007 1.x Errata February 8, 2007. This is a companion specification to the PCI Express. View more This is a companion specification to the PCI Express Base Specification.
Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 2.5 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications. Show less 1.x Specification January 4, 2007. This specification is a companion for the PCI Expres.
View more This specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications.
The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications. Show less 1.x Specification March 28, 2005.
This specification is a companion for the PCI Expres. View more This specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications.
Show less 1.x Specification March 28, 2005. This document is a companion specification to the PC. View more This document is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of a modular I/O form factor that is focused on the needs of workstations and servers from mechanicals and electrical requirements. The discussions are confined to the modules and their chassis slots requirements.
Other form factors are covered in other separate specifications. Show less 1.x Specification February 14, 2005. This ECR proposes a mechanism (new extension to DSM. View more This ECR proposes a mechanism (new extension to DSM) to make the device names/labels under Operating Systems deterministic. Currently, there is no well defined mechanism to consistently associate platform specific device names and instances of a device type under operating system. As a result, instance labels for specific device types under various operating systems (ex: ethx label for networking device instance under Linux OS) do not always map into the platform designated device labels. Additionally, the instance labels can change based on the system configuration.
For example, under Linux operating systems, the “eth0” label does not necessarily map to the first embedded networking device as designed in a given platform. Depending on the hardware bus topology, current configuration including the number and type of networking adapters installed, the eth0 label assignment could change in a given platform. Show less 3.x ECN March 28, 2010. A number of PCIe base specifications ECNs have been. View more A number of PCIe base specifications ECNs have been approved that require software support. In some cases, platform firmware needs to know if the OS running supports certain features, or the OS needs to be able to request control of certain features from platform firmware. In other cases, the OS needs to know information about the platform that cannot be discovered through PCI enumeration, and ACPI must be used to supply the additional information.
Show less 3.x ECN February 1, 2010. Changes are to the PCI Standard Hot-Plug Controller. View more Changes are to the PCI Standard Hot-Plug Controller and Subsystem Specification, Revision 1.0. This ECN extends the Standard Hot-plug Controller Specification to support the additional PCI-X speeds and modes allowed by the PCI-X 2.0 specification.
Specifically, this ECN provides the required hardware and software extensions needed to support the new PCI-X 2.0 speeds of 266 and 533 and also the software extensions needed to control PCI-X 2.0 mode ECC and parity operation. Show less 1.x ECN February 27, 2003. The intent of this ECR is to update the PCI base spe. View more The intent of this ECR is to update the PCI base specifications to include PCI connector metallurgical practices which have been commonly accepted or introduced since the original wording was drafted before the PCI 2.0 specification. With an overwhelming majority of PCI and PCI-X connectors shipped in the world that do not meet the PCI specification for contact finish plating, the most efficient way to rectify the situation is to correct the specification. Show less 2.x ECN January 7, 2003. The intent of this ECR is to update the PCI base spe.
View more The intent of this ECR is to update the PCI base specifications to include PCI connector metallurgical practices which have been commonly accepted or introduced since the original wording was drafted before the PCI 2.0 specification. With an overwhelming majority of PCI and PCI-X connectors shipped in the world that do not meet the PCI specification for contact finish plating, the most efficient way to rectify the situation is to correct the specification. Show less 3.x ECN January 7, 2003.